In order to transfer data between individual units of a data-processing system, such as a processor unit and a peripheral unit, the individual units are each provided with serial interface units via which the data can be transmitted and from which the data can be received. The data transfer is thereby synchronous, which means that one of the units involved, the so-called master unit, generates a clock signal which, for the purpose of controlling the corresponding data transfer process, is passed on to the units connected to the system. In the specific technical literature, a serial interface unit of this type is known as an SPI (for serial peripheral interface). Such an interface unit is provided with a transmit shift register from which the data are serially transmitted to a data output via an output driver. The data output is then connected to the data input of the peripheral unit for which the data are meant. For the purpose of receiving the data, the serial interface unit contains a receive shift register into which the data received at a data input are fed serially. The serial data thereby come from the data output of that serial interface unit of the peripheral unit to which they were applied from its transmit shift register via an output driver.
To ensure a correct data transfer, extensive handshaking procedures and checksum transfers are currently carried out, whereby the receiver of the corresponding data must confirm that the data have been correctly received by returning a corresponding acknowledge message. These procedures necessitate an increased expenditure in terms of hardware and software for the units involved in the transfer of the data, and the volume of the transferred data is furthermore increased. All these factors contribute to a reduction of the attainable data transmission speed.